1. Field of the Invention
The present invention relates to circuitry for and a method of generating vertical drive pulses in a video signal receiver, and more particularly, it relates to circuitry for and a method of regularly correctly generating vertical drive pulses for video signal broadcasting systems having different cycles of vertical synchronizing signals.
2. Description of the Background Art
A television receiver extracts horizontal and vertical synchronizing signals from a received video signal and performs horizontal and vertical scanning on a display screen (CRT: cathode ray tube) in synchronization with the extracted horizontal and vertical synchronizing signals.
If the vertical synchronizing signal is dropped out for a short period by a weak electric field etc. or spurious noise is caused in a vertical blanking period, a step-out state (out-of-synchronization state) in a vertical direction, instability in vertical synchronization, incomplete interlace scanning and the like may be caused.
A vertical synchronization circuit of a countdown system is well known as circuit structure for removing the aforementioned disadvantages.
FIG. 1 schematically illustrates overall structure of a television receiver which employs a conventional vertical synchronization circuit of the countdown system. Referring to FIG. 1, Y/C processing circuit (luminance/chrominance processing circuit), a VIF (video signal intermediate frequency detector/amplifier), an SIF (sound signal intermediate frequency amplifying circuit) and a vertical/horizontal deflection circuit parts are integrally formed on one IC (integrated circuit). A tuner selects a video signal of a desired frequency band from a high-frequency signal received through an antenna 14, and supplies the same to a VIF (video intermediate frequency signal detector/amplifier) 2. A video signal intermediate frequency signal derived from the VIF 2 is processed in three circuit parts.
The first circuit part is to derive a sound signal, and includes an SIF 9 which receives the output from the VIF 2 for detecting and amplifying the sound intermediate frequency signal. The output rom the SIF 9 is supplied to a speaker 13.
The second circuit part is to process a luminance signal and a chrominance signal for deriving desired chrominance signals of red (R), green (G) and blue (B), and is formed by a Y/C processing circuit 4. The output of the Y/C processing circuit 4 is supplied to a CRT 10.
The third circuit part is to separate horizontal and vertical synchronizing signals included in a composite video signal from the VIF 2, thereby to derive signals for defining horizontal and vertical scanning periods in the CRT 10 on the basis of respective separated and extracted horizontal and vertical synchronizing signals. This circuit part includes a sync separation circuit 3 which separates and extracts the horizontal and vertical synchronizing signals included in the composite video signal from the VIF 2.
A circuit part for deriving the vertical synchronizing signal includes a vertical drive pulse generator 5 which extracts the vertical synchronizing signal from the synchronizing signals received from the sync separation circuit 3 and generates a vertical drive pulse corresponding to the vertical synchronizing signal and a vertical deflection circuit 6 which generates a sawtooth-like signal in response to the vertical drive pulse from the vertical drive pulse generator 5. The output from the vertical deflection circuit 6 is supplied to a vertical deflection coil 11.
A circuit part for defining horizontal scanning is formed by a horizontal AFC circuit 7 which extracts the horizontal synchronizing signal from the synchronizing signals received from the sync separation circuit 3 and extracts a horizontal synchronizing pulse signal corresponding to the extracted horizontal synchronizing signal and a horizontal deflection circuit 8 which generates a sawtooth-like pulse signal for defining a horizontal scanning period in response to the horizontal synchronizing pulse signal received from the horizontal AFC circuit 7. The output from the horizontal deflection circuit 8 is supplied to a horizontal deflection coil 12.
The vertical drive pulse generator 5 includes a vertical synchronizing signal separation circuit 21 which separates and extracts the vertical synchronizing signal from the synchronizing signals extracted by the sync separation circuit 3 and a vertical countdown counter circuit 22 which divides a frequency 2 f.sub.H (f.sub.H : horizontal scanning frequency, i.e., frequency of the horizontal synchronizing signal of about 15.7 KHz) supplied from the horizontal AFC circuit 7 and generates the vertical drive pulse in response to the signal from the vertical synchronizing signal separation circuit 21.
The horizontal AFC circuit 7 is adapted to derive a signal having a frequency corresponding to the horizontal synchronizing signal from the synchronizing signals separated by the sync separation circuit 3. This horizontal AFC circuit 7 includes a phase comparator 23 which compares the phases of the signal from the sync separation circuit 3 and the output from a 1/2 frequency divider 26, a low-pass filter 24 which passes a low-frequency component of the output from the phase comparator 23, a voltage controlled oscillator 25 which changes its oscillation frequency in response to the output from the low-pass filter 24, and the 1/2 frequency divider 26 which frequency-divides the output of the voltage controlled oscillator 25 and outputs the same. The central oscillation frequency of the voltage controlled oscillator 25 is set at 2 f.sub.H. This horizontal AFC circuit 7 forms a PLL. Such circuit structure for generating a vertical drive pulse through a vertical countdown counter circuit is shown in U. S. Pat. No. 4,231,064 and European Patent application publication No. 249987A2, for example. These prior arts show circuit structure which shapes a vertical synchronizing signal into correctly defined pulse width even if noise is caused at immediately precede the vertical synchronizing signal.
This countdown system takes the advantage of the fact that there is a fixed relation between a horizontal scanning cycle and a vertical scanning cycle (cycle of a vertical synchronizing signal). The ratio of the vertical scanning cycle to the horizontal scanning cycle is 2:525 in the NTSC system, while this ratio is mainly 2:625 in the PAL and SECAM systems. Such a prescribed ratio is employed to frequency-divide a stably generated horizontal synchronizing signal and to generate a vertical drive pulse in correspondence to a prescribed vertical synchronizing signal.
In the prior art structure, the output of a vertical sync separation circuit is passed through a gate circuit only for a prescribed period in response to the output of a counter circuit which frequency-divides a clock signal corresponding to a horizontal synchronizing signal. In the prior art, the phase of an externally supplied vertical synchronizing signal is compared with that of a timing signal outputted from the counter, to reset the counter circuit by the external vertical synchronizing signal and generate a vertical drive pulse or to reset the counter circuit by a timing signal from a counter on the basis of the result of such phase comparison. When the phase of the external vertical synchronizing signal is varied in special reproduction mode in a VCR (video cassette recorder), for example, the counter circuit is reset by the externally supplied vertical synchronizing signal all the time.
Increasingly and widely employed is circuit structure which can be commonly applied to two different broadcasting systems (NTSC and PAL systems), as shown in Japanese Patent Laying-Open Gazette No. 193679/1984, for example. This prior art discloses structure of discriminating the broadcasting system by deciding the cycle of an externally supplied vertical synchronizing signal through phase difference between the output of a counter circuit and the vertical synchronizing signal.
FIG. 2 schematically illustrates the structure of a gate circuit part in a conventional apparatus for automatically discriminating a television broadcasting system. The part shown in FIG. 2 corresponds to the part of the vertical countdown counter circuit 22 shown in FIG. 1. Referring to FIG. 2, a vertical drive pulse generator (vertical countdown counter circuit 22) includes a counter circuit 32, a gate circuit 34 and a reset pulse generator 35. The counter circuit 32 receives a horizontal synchronizing signal supplied through an input terminal 31 at its clock input CL and frequency-divides the horizontal synchronizing signal, to generate a signal in predetermined timing. The gate circuit 34 passes a vertical synchronizing signal supplied through another input terminal 33 in response to a control signal supplied from the counter circuit 32. The reset pulse generator 35 generates a reset pulse RST for resetting the counter circuit 32 in response to the vertical synchronizing signal from the gate circuit 34.
The counter circuit 32 is reset in response to the reset pulse RST from the reset pulse generator 35, and thereafter re-counts the horizontal synchronizing signal supplied from the input terminal 31. The counter circuit 32 shuts off the gate circuit 34 up to a period in which arrival of an external vertical synchronizing signal is expected, thereby to prevent the circuits of subsequent stages from adverse influence exerted by noise from the input terminal 33 or the like. Operation is now briefly described.
The counter circuit 32 counts the horizontal synchronizing signal (corresponding to a clock signal having a frequency f.sub.H, which is 1/2 of the frequency 2 f.sub.H supplied from the horizontal AFC circuit 7 shown in FIG. 1) received from the input terminal 31. When the count n reaches 240, at which arrival of a vertical synchronizing signal of the NTSC or PAL system is expected, the counter circuit 32 generates a gate signal for electrically opening the gate circuit 34. If a normal vertical synchronizing signal is supplied to the gate circuit 34 through the input terminal 33 in this state, the vertical synchronizing signal of the NTSC system or that of the PAL system is passed through the gate circuit 34 and supplied to the pulse generator 35 at timing of n=262.5 or n=312.5. Hence, the pulse generator 35 generates the reset pulse RST in response to the supplied vertical synchronizing signal and supplies the same to the counter circuit 32. The counter circuit 32 generates a vertical drive pulse in response to the reset pulse RST, and supplies the same to a vertical deflection circuit (6 in FIG. 1). The counter circuit 32 is reset by the reset pulse RST and then resumes counting the horizontal synchronizing signal, to repeat operation similar to the above.
When no vertical synchronizing signal is supplied to the input terminal 33, the counter circuit 32 generates a pulse at n=340, and supplies the same to the reset pulse generator 35. The reset pulse generator 35 generates a reset pulse in response to this control signal received from the counter circuit 32 at n=340 , and resets the counter circuit 32. Thus, the counter circuit 32 enters a self-reset state (a state reset by the control signal generated from the counter itself). In this state the television picture flows vertically since generation timing of the vertical drive pulse for the television picture corresponds to n=340. Identification of the broadcasting system is performed by phase comparison of the output of the gate circuit 34 and a pulse signal generated at n=240 or 288 from the counter circuit 32.
According to the circuit structure shown in FIG. 2, the circuits of subsequent stages can be prevented from malfunctions by noise caused by a weak electric field or the like included in a composite video signal by opening the gate circuit 34 only for a specific period with respect to the externally supplied vertical synchronizing signal.
In the structure shown in FIG. 2, the gate circuit 34 is adapted to be commonly employable for both the NTSC and PAL broadcasting systems. Therefore, starting of a gate period for opening the gate circuit 34 is set at the timing of n=240, since the vertical synchronizing signal of the NTSC system generally arrives at n=262.5. However, when the vertical synchronizing signal of the PAL system is received, noise immunity is deteriorated if the gate circuit 34 is opened at n=240 since this vertical synchronizing signal normally arrives at n=312.5. When noise is caused in the video signal of the PAL system to appear in a position preceding generation timing of the vertical synchronizing signal, the noise is passed through the gate circuit 34 to cause a malfunction of the counter circuit 32.
Japanese Patent Laying-Open Gazette No. 193679/1984 discloses structure of setting the opening period of the gate circuit 34 within a range of 244 H to 287 H (H: one horizontal scanning period) for the NTSC system and within a range of 288 H to 340 H for the PAL system. In this prior art, however, a critical point for discrimination between the PAL and NTSC systems is set between 287 H and 288 H, and hence the broadcasting system cannot be discriminated if the vertical synchronizing signal is generated in this boundary region in special playing mode of a VCR, for example, or the vertical synchronizing signal is cyclically varied in the vicinity of the discrimination critical point. Thus, the vertical drive pulse may be generated in accordance with an erroneous broadcasting system to cause vertical flow of the picture due to a step-out phenomenon.
U.S. Pat. No. 4,489,343 discloses structure in which periods for opening the gate circuit are varied with the NTSC and PAL systems. In this prior art, the gate period is 240 H to 288 H in the NTSC system and 288 H to 352 H in the PAL system in VCR playing mode. On the other hand, the gate period is set in a range of 256 H to 272 H in the NTSC system and in a range of 304 H to 320 H in the PAL system in receiving of broadcasting signals. In this prior art, however, when a vertical synchronization signal is generated in the range for the NTSC system (below 288 H), the counter circuit is reset at counting of 352, and hence synchronization is instabilized to cause vertical flow of the picture.